Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Remembrance of circuits past: macromodeling by data mining in large analog design spaces
Proceedings of the 39th annual Design Automation Conference
Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Cost Analog Testing of RF Signal Paths
Proceedings of the conference on Design, automation and test in Europe - Volume 1
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Low-cost testing of 5 GHz low noise amplifiers using new RF BIST circuit
Journal of Electronic Testing: Theory and Applications
Test Development Through Defect and Test Escape Level Estimation for Data Converters
Journal of Electronic Testing: Theory and Applications
A Low-Noise Amplifier with Integrated Current and Power Sensors for RF BIST Applications
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Practices in Mixed-Signal and RF IC Testing
IEEE Design & Test
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing
Journal of Electronic Testing: Theory and Applications
A general method to evaluate RF BIST techniques based on non-parametric density estimation
Proceedings of the conference on Design, automation and test in Europe
Defect level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal testing of VLSI analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing analog and mixed-signal integrated circuits using oscillation-test method
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A comprehensive signature analysis scheme for oscillation-test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic Probability Extraction for Nonnormal Performance Distributions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect-Oriented Testing of RF Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quadratic Statistical Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical parametric test metrics estimation: a ΣΔ converter BIST case study
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Assessment of Microfluidic System Testability using Fault Simulation and Test Metrics
Journal of Electronic Testing: Theory and Applications
On proving the efficiency of alternative RF tests
Proceedings of the International Conference on Computer-Aided Design
Analog test metrics estimates with PPM accuracy
Proceedings of the International Conference on Computer-Aided Design
Multidimensional analog test metrics estimation using extreme value theory and statistical blockade
Proceedings of the 50th Annual Design Automation Conference
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We present a method that is capable of handling process variations to evaluate analog/RF test measurements at the design stage. The method can readily be used to estimate test metrics, such as parametric test escape and yield loss, with parts per million accuracy, and to fix test limits that satisfy specific tradeoffs between test metrics of interest. Furthermore, it provides a general framework to compare alternative test solutions that are continuously being proposed toward reducing the high cost of specification-based tests. The key idea of the method is to build a statistical model of the circuit under test and the test measurements using nonparametric density estimation. Thereafter, the statistical model can be simulated very fast to generate an arbitrarily large volume of new data. The method is demonstrated for a previously proposed built-in self-test measurement for low-noise amplifiers. The result indicates that the new synthetic data have the exact same structure of data generated by a computationally intensive brute-force Monte Carlo circuit simulation.