Rapid frequency-domain analog fault simulation under parameter tolerances
DAC '97 Proceedings of the 34th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Integrated Design and Test of Mixed-Signal Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
A parametric test method for analog components in integrated mixed-signal circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ON-CHIP MEASUREMENT OF THE JITTER TRANSFER FUNCTION OF CHARGE-PUMP PHASE-LOCKED LOOPS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Control and Observation Structure for Analog Circuits with Current Test Data
Journal of Electronic Testing: Theory and Applications
A simple built-in current sensor for IDDQ testing of CMOS data converters
Integration, the VLSI Journal
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Analytical approach for testing linking-with-light circuits and systems
IMACS'08 Proceedings of the 7th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
WSEAS Transactions on Circuits and Systems
Evaluation of analog/RF test measurements at the design stage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple built-in current sensor for IDDQ testing of CMOS data converters
Integration, the VLSI Journal
Automatic linearity and frequency response tests with built-in pattern generator and analyzer
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault analysis and simulation of large scale industrial mixed-signal circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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The high cost of capital equipment for production testing coupled with the time that an analog circuit spends on a tester has made it imperative to minimize average chip testing time during production. Testing time can be reduced by decreasing the number of tests that need to be performed on a circuit and by optimizing the order of the tests. This can be done by studying performance data for a sample of chips or using simulation data. The advantage of simulation data is that a large number of circuits do not have to be nonoptimally tested in order to generate the data set. Generating simulation data for very large scale integration (VLSI) analog circuits has been considered to be very difficult because of the computational cost of simulating a large system, the very large number of random variables needed to model the manufacturing process, and the need to model and simulate not only random parameter variations but also spot defects. These problems are overcome by decomposing a circuit into several blocks, which are linked together by a behavioral model of the system. In order for this to work, the blocks must not depend on a large set of significant random variables, and the blocks should not be tightly coupled. In this paper we demonstrate our statistical simulation methodology for a VLSI analog circuit. The proposed approach to defect simulation is applied to a parallel filter bank which has a total of 32 channels, is composed of 67 blocks, and has over 4040 transistors and 750 capacitors. Simulation results are used to optimize the test set for this circuit, by showing that the frequency response tests at many frequencies are redundant