Behavioral Level Noise Modeling and Jitter Simulation ofPhase-Locked Loops with Faults Using VHDL-AMS

Authors:
Nihal J. Godambe;C.-J. Richard Shi
Affiliations:
Wireless Integrated Technology Center, Motorola, Ft. Lauderdale, FL 33322. E-mail: nihal@email.mot.com;Department of Electrical Engineering, University of Washington, Seattle, WA 98195. E-mail: cjshi@ee.washington.edu
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
1998

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Abstract

It is important to predict noise at the early stages of a top-down design.In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops,using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at thebehavioral level.In contrast to existing approaches which either require dedicated noise simulators orpostpone noise and fault simulation to the transistor level,we have successfully demonstrated thatnoise in a voltage-controlled oscillator (VCO),power supply noise,and their effects on the overall phase jitter within a faulty PLL can be modeled and simulated earlier on at the behavioral level. Our simulation results areconsistent with experimentally-verified theoretical predictions.