FSPICE: a tool for fault modelling in MOS circuits
Integration, the VLSI Journal
Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A methodology for testability enhancement at layout level
Journal of Electronic Testing: Theory and Applications
IC Defects-Based Testability Analysis
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Physical DFT for High Coverage of Realistic Faults
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Rapid frequency-domain analog fault simulation under parameter tolerances
DAC '97 Proceedings of the 34th annual Design Automation Conference
SWITTEST: automatic switch-level fault simulation and test evaluation of switched-capacitor systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Fault Simulation for Analog Circuits Under Parameter Variations
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from ECS '97
Analog Testing with Time Response Parameters
IEEE Design & Test
Fast Fault Simulation for Nonlinear Analog Circuits
IEEE Design & Test
Defect-Oriented Experiments in Fault Modelling and Fault Simulation of Microsystem Components
EDTC '96 Proceedings of the 1996 European conference on Design and Test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
17.2 A Design for Testability Study on a High Performance Automatic Gain Control Circuit
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Speed-up of High Accurate Analog Test Stimulus Optimization
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-based test optimization for analog/RF circuits for near-zero DPPM applications
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Block-level Bayesian diagnosis of analogue electronic circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Fault analysis and simulation of large scale industrial mixed-signal circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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A comprehensive tool has been implemented for the comparison of different test preparation techniques and target faults. It comprises of the realistic fault characterisation program LIFT that can extract sets of various faults from a given analogue or mixed-signal circuit layout and the automatic analogue fault simulation program AnaFAULT which can handle arbitrary catastrophic and parametric faults. For a fabricated integrated VCO circuit the capabilities of the tool are demonstrated and simulation results are presented.