Logic testing and design for testability
Logic testing and design for testability
Yield simulation for integrated circuits (fault analysis, redundancy analysis, fabrication defects)
Yield simulation for integrated circuits (fault analysis, redundancy analysis, fabrication defects)
Metrics, techniques and recent developments in mixed-signal testing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Symbolic Handling of Bridging Fault Effects
Journal of Electronic Testing: Theory and Applications
Efficient modeling of switch-level networks containing undetermined logic node states
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the design of self-checking functional units based on Shannon circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Bridging Faults in Pipelined Circuits
Journal of Electronic Testing: Theory and Applications
On the properties of the input pattern fault model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Switch-level bridging fault simulation in the presence of feedbacks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Power supply current detectability of SRAM defects
ATS '95 Proceedings of the 4th Asian Test Symposium
Deterministic test generation for non-classical faults on the gate level
ATS '95 Proceedings of the 4th Asian Test Symposium
A simple technique for locating gate-level faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Correlation between I/sub DDQ/ testing quality and sensor accuracy
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A fault diagnosis methodology for the UltraSPARC/sup TM/-I microprocessor
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A new quality estimation methodology for mixed-signal and analogue ICs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Fast Algorithms for Computer IDDQ Tests for Combination Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Switch-level modeling of feedback faults using global oscillation control
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
ITC '97 Proceedings of the 1997 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
Journal of Electronic Testing: Theory and Applications
Fault Simulation of IDDQ Tests for Bridging Faults in Sequential Circuits
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An approach to the analysis and test of crosstalk faults in digital VLSI circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Resistive bridging fault simulation of industrial circuits
Proceedings of the conference on Design, automation and test in Europe
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A test methodology to support an ASEM MCM foundry
ITC'94 Proceedings of the 1994 international conference on Test
Analogue fault simulation based on layout dependent fault models
ITC'94 Proceedings of the 1994 international conference on Test
Back annotation of physical defects into gate-level, realistic faults in digital ICs
ITC'94 Proceedings of the 1994 international conference on Test
Simulation results of an efficient defect analysis procedure
ITC'94 Proceedings of the 1994 international conference on Test
Analysis of experimental results on functional testing and diagnosis of complex circuits
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Extraction and simulation of realistic CMOS faults using inductive fault analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
| Hi-index | 0.00 |
Functional failures of VLSI circuits are caused by process-induced defects. Such defects have very complex physical characteristics and may be significantly different from the simplistic defect models assumed by typical fault modeling techniques. In the tutorial an overview of the actual mechanisms causing processing defects, and the defects' electrical manifestations will be discussed. It will be demonstrated that inadequate insight into the physics of processing defects and the manufacturing process may lead to inefficient testing of actual VLSI circuits.