Analogue fault simulation based on layout dependent fault models

Authors:
R. J. A. Harvey;A. M. D. Richardson;E. M. J. G. Bruls;K. Baker
Affiliations:
Engineering Department, Lancaster University, Lancaster, UK;Engineering Department, Lancaster University, Lancaster, UK;Philips Research Laboratorie, Eindhoven, NL;Philips Research Laboratorie, Eindhoven, NL
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

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Abstract

A testability analysis procedure for complex analogue circuits is presented based on layout dependent fault models extracted from process defect statistics. The technique has been applied to a mixed-signal phase locked loop circuit and a number of test methodologies have been evaluated including the existing production test. It is concluded that the fault coverage achieved by this test can be improved by the use of a supplementary test based on power supply variations.