Very-Low-Voltage Testing for Weak CMOS Logic ICs

RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage

Journal of Electronic Testing: Theory and Applications

Real-Time Current Testing for A/D Converters

IEEE Design & Test

Performance Comparison of VLV, ULV, and ECR Tests

Journal of Electronic Testing: Theory and Applications

Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Toward understanding "Iddq-only" fails

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Detecting resistive shorts for CMOS domino circuits

ITC '98 Proceedings of the 1998 IEEE International Test Conference

CMOS IC reliability indicators and burn-in economics

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers

Journal of Electronic Testing: Theory and Applications

A design-for-test structure for optimising analogue and mixed signal IC test

EDTC '95 Proceedings of the 1995 European conference on Design and Test

SHOrt voltage elevation (SHOVE) test for weak CMOS ICs

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Bridges in sequential CMOS circuits: current-voltage signature

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

2.1 Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Testing High Speed VLSI Devices Using Slower Testers

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Testing for Tunneling Opens

ITC '00 Proceedings of the 2000 IEEE International Test Conference

DELAY-FAULT TESTING AND DEFECTS IN DEEP SUB-MICRON ICS - DOES CRITICAL RESISTANCE REALLY MEAN ANYTHING?

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Stuck-Fault Tests vs. Actual Defects

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Test Method Evaluation Experiments & Data

ITC '00 Proceedings of the 2000 IEEE International Test Conference

An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Practical Application of Energy Consumption Ratio Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Resistive Bridge Fault Modeling, Simulation and Test Generation

ITC '99 Proceedings of the 1999 IEEE International Test Conference

1998 ITC Best Paper: Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment

ITC '99 Proceedings of the 1999 IEEE International Test Conference

A DFT Technique for High Performance Circuit Testing

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Testing and Reliability Techniques for High-Bandwidth Embedded RAMs

Journal of Electronic Testing: Theory and Applications

The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

IDDX-based test methods: A survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)

DFT for Delay Fault Testing of High-Performance Digital Circuits

IEEE Design & Test

Low Voltage Test in Place of Fast Clock in DDSI Delay Test

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip

Journal of Electronic Testing: Theory and Applications

On test conditions for the detection of open defects

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Timing-based delay test for screening small delay defects

Proceedings of the 43rd annual Design Automation Conference

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A novel framework for faster-than-at-speed delay test considering IR-drop effects

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs

Proceedings of the conference on Design, automation and test in Europe

Small-delay defect detection in the presence of process variations

Microelectronics Journal

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Diagnosis of multiple-voltage design with bridge defect

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A novel faster-than-at-speed transition-delay test method considering IR-drop effects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Defect classes - an overdue paradigm for CMOS IC testing

ITC'94 Proceedings of the 1994 international conference on Test

Variable supply voltage testing for analogue CMOS and bipolar circuits

ITC'94 Proceedings of the 1994 international conference on Test

Analogue fault simulation based on layout dependent fault models

ITC'94 Proceedings of the 1994 international conference on Test

Simulation results of an efficient defect analysis procedure

ITC'94 Proceedings of the 1994 international conference on Test

Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-level impact of chip-level failure mechanisms and screens

Proceedings of the International Conference on Computer-Aided Design

Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels

Proceedings of the Conference on Design, Automation and Test in Europe