Accelerated transition fault simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
At-speed delay testing of synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A rated-clock test method for path delay faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generating Tests for Delay Faults in Nonscan Circuits
IEEE Design & Test
High-Performance Circuit Testing with Slow-Speed Testers
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Techniques for Characterizing DRAMs With a 500-MHz Interface
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Path Delay Testing: Variable-Clock Versus Rated-Clock
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
IEEE Design & Test
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Journal of Electronic Testing: Theory and Applications
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths
Journal of Electronic Testing: Theory and Applications
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The speed of new VLSI designs is rapidly increasing. Assuring the performance of the circuit requires that the circuit be tested at its intended operating speed. The high cost of high speed testers makes it impossible for the testers to follow the designs in terms of speed increase. This gap between the speed of the new circuits and the speed of the testers is not likely to disappear. In this paper, we focus on at-speed strategies for testing high speed designs on slower testers. Conventional at-speed testing strategies assume that the primary inputs/outputs can be applied/observed at the circuit rated speed. This requires a high speed tester. Our assumption is that a fast clock matching the speed of the designs is available. We describe two classes of at-speed strategies that can be used on a low speed tester. The first class consists of testing schemes for which the test generation procedure is independent of the speed of the tester. These methods apply multiple input patterns in one tester cycle and the test class of at-speed testing schemes integrate the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. We present preliminary experimental results for at-speed schemes for slow testers for transition faults.