Gross delay defect evaluation for a CMOS logic design system product
IBM Journal of Research and Development
Delay test of chip I/Os using LSSD boundary scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Compact two-pattern test set generation for combinational and full scan circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Generation of tenacious tests for small gate delay faults in combinational circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Improving accuracy in path delay fault coverage estimation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On test coverage of path delay faults
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Effects of Multi-cycle Sensitization on Delay Tests
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testing High Speed VLSI Devices Using Slower Testers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Multiple-Output Propagation Transition Fault Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Case Study on t e Implementation of t e Illinois Scan Architecture
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Study of Test Quality/Tester Scan Memory Trade-offs Using the SEMATECH Test Methods Data
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On Reducing Peak Current and Power during Test
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Quality Transition Fault Tests Suitable for Small Delay Defects
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Delay Fault Diagnosis for Non-Robust Test
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion
IEEE Design & Test
Layout-aware scan chain reorder for launch-off-shift transition test coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transition faults detection in bit parallel multipliers over GF(2m)
WSEAS Transactions on Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-aware multiple-delay-fault diagnosis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Balancing structured and ad-hoc design for test: testing of the PowerPC 603TMmicroprocessor
ITC'94 Proceedings of the 1994 international conference on Test
Delay test generation 1: concepts and coverage metrics
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 2: algebra and algorithms
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Test generation in systolic architecture for multiplication over GF(2m)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selection of a fault model for fault diagnosis based on unique responses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed-state tests for delay faults in scan designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical defect-detection analysis of test sets using readily-available tester data
Proceedings of the International Conference on Computer-Aided Design
Flip-flop selection for partial enhanced scan to reduce transition test data volume
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
AC-plus scan methodology for small delay testing and characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions,such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patternsand simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern,single-fault propagation, is an efficient way to simulate delay faults. The authors describe results from 10 benchmark designsand discuss add-ons to a stuck fault simulator to enable transition fault simulation. Their experiments show that delay faultsimulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.