DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Quality considerations in delay fault testing
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Vector Generation for Parametric Path Delay Faults
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A diagnosability metric for parametric path delay faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On the effects of test compaction on defect coverage
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On the decline of testing efficiency as fault coverage approaches 100%
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
IEEE Design & Test
Design-for-testability for path delay faults in large combinational circuits using test points
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On diagnosis of pattern-dependent delay faults
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple-Output Propagation Transition Fault Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Autonomic Microprocessor Execution via Self-Repairing Arrays
IEEE Transactions on Dependable and Secure Computing
Generation of broadside transition fault test sets that detect four-way bridging faults
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
EDA solutions to new-defect detection in advanced process technologies
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We study the effectiveness of n-detection test sets based on sition faults in detecting defects that affect the timing behavior of a circuit. We use path delay faults as surrogates for unmodeled defects, and show that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased. We also introduce a method to reduce the number of tests included in an n-detection test set by using different values n for different faults based on their potential effect on the defect coverage. The resulting test sets are referred to as variable n-detection test sets.