Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
IEEE Transactions on Computers
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Fast sequential circuit test generation using high-level and gate-level techniques
Proceedings of the conference on Design, automation and test in Europe
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits
ATS '99 Proceedings of the 8th Asian Test Symposium
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
A Fault Model for Function and Delay Testing
ETW '01 Proceedings of the IEEE European Test Workshop (ETW'01)
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets
PRDC '02 Proceedings of the 2002 Pacific Rim International Symposium on Dependable Computing
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Properties of the input pattern fault model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Derivation of Minimum Test Sets for Unate Logical Circuits
IEEE Transactions on Computers
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The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. In this paper we consider the realization-independent testing and the impact of circuit realization on the fault coverage. We investigated two fault models (input-output pin pair fault and input-input-output pin triplet fault) that are used by test generation for circuits described at system description level. The test generation on the system-level model is preferable if the efforts and the duration of the test supplement activities are less than the efforts and the duration of the test generation on gate-level model. The test set for the black-box model is larger as compared to the test set for the particular realization of the circuit. However, large test sets for the black-box model can be compacted by analysis not only according to the stuck-at faults, but also according to various defects for the particular realization.