Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Modeling and Simulation of Design Errors
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Toward formalizing a validation methodology using simulation coverage
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automatic test bench generation for simulation-based validation
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Automatic test bench generation for validation of RT-level descriptions: an industrial experience
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Functional test generation for behaviorally sequential models
Proceedings of the conference on Design, automation and test in Europe
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
A data flow fault coverage metric for validation of behavioral HDL descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On Design Validation Using Verification Technology
Journal of Electronic Testing: Theory and Applications
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Automatic Validation of Protocol Interfaces Described in VHDL
Real-World Applications of Evolutionary Computing, EvoWorkshops 2000: EvoIASP, EvoSCONDI, EvoTel, EvoSTIM, EvoROB, and EvoFlight
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Simplifying Boolean constraint solving for random simulation-vector generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
System-Level Test Bench Generation in a Co-Design Framework
ETW '00 Proceedings of the IEEE European Test Workshop
12.1 Using Verification Technology for Validation Coverage Analysis and Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Validation Fault Model for Timing-Induced Functional Errors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Redundant functional faults reduction by saboteurs synthesis [logic verification]
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Event-driven observability enhanced coverage analysis of C programs for functional validation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A coverage metric for the validation of interacting processes
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A framework for the functional verification of systemC models
International Journal of Parallel Programming
An efficient evaluation and vector generation method for observability-enhanced statement coverage
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Clock domain crossing fault model and coverage metric for validation of SoC design
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 20th annual conference on Integrated circuits and systems design
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
Post-silicon is too late avoiding the $50 million paperweight starts with validated designs
Proceedings of the 47th Design Automation Conference
Using model-based test program generator for simulation validation
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Observable modified Condition/Decision coverage
Proceedings of the 2013 International Conference on Software Engineering
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Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the designer simulates the design using a large number of vectors attempting to debug and verify the design. A major problem with functional simulation is the lack of good metrics and tools to evaluate the quality of a set of functional vectors. Metrics used currently are based on instruction counts and are quite simplistic. Designers are forced to use ad-hoc methods to terminate functional simulation, e.g. CPU time limitations. We propose a new metric for measuring the extent of design verification provided by a set of functional simulation vectors. This metric is universal, and can be used uniformly for all designs. Our metric computes observability information to determine whether effects of errors that are activated by the program stimuli can be observed at the circuit outputs. We provide preliminary experimental evidence that supports the validity of the proposed metric. We believe that using this metric in design verification will result in higher-quality functional checking. tests and improved correctness