Selecting Software Test Data Using Data Flow Information
IEEE Transactions on Software Engineering
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
The VERILOG PLI Handbook: A User's Guide and Comprehensive Reference on the VERILOG Programming Language Interface
A data flow fault coverage metric for validation of behavioral HDL descriptions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Journal of Electronic Testing: Theory and Applications
OCCOM-efficient computation of observability-based code coverage metrics for functional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Simulation is still the primary verification method for integrated circuit designs, and coverage evaluation is indispensable for it on account of its incompleteness. As the functional complexity of modern designs is increasing dramatically, it is necessary to take observability into consideration for coverage metrics. In this paper we extend factored use-definition chains (FUD chains), a mature data structure in compilers, from sequential software to concurrent hardware design, and propose dynamic FUD chains (DFUD chains). Based on it, we present an observability model and an algorithm to evaluate observability-based statement coverage. This technique has several advantages. Firstly, it could be easily integrated into compilers or simulators for hardware description languages, since it utilizes many flow analysis techniques adopted in compilers. Secondly, it can be combined with many controllability metrics, such as statement coverage metric, since the observability model is based on definitions and uses of variables. The proposed technique has been implemented as a prototype tool for Verilog designs, and experimental results show its benefits.