Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Automatic test bench generation for validation of RT-level descriptions: an industrial experience
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testability Analysis and ATPG on Behavioral RT-Level VHDL
Proceedings of the IEEE International Test Conference
RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs
ETW '00 Proceedings of the IEEE European Test Workshop
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
High-Level Observability for Effective High-Level ATPG
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
An evolutionary algorithm for reducing integrated-circuit test application time
Proceedings of the 2002 ACM symposium on Applied computing
A fast, inexpensive and scalable hardware acceleration technique for functional simulation
Proceedings of the 39th annual Design Automation Conference
Initializability analysis of synchronous sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
Journal of Electronic Testing: Theory and Applications
Evolutionary Techniques for Minimizing Test Signals Application Time
Proceedings of the Applications of Evolutionary Computing on EvoWorkshops 2002: EvoCOP, EvoIASP, EvoSTIM/EvoPLAN
ARPIA: A High-Level Evolutionary Test Signal Generator
Proceedings of the EvoWorkshops on Applications of Evolutionary Computing
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Improved SAT-based Bounded Reachability Analysis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A novel RTL behavioral description based ATPG method
Journal of Computer Science and Technology
Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Pipelining Sequential Circuits with Wave Steering
IEEE Transactions on Computers
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Considering Circuit Observability Don't Cares in CNF Satisfiability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
A new incremental placement algorithm and its application to congestion-aware divisor extraction
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
A coverage metric for the validation of interacting processes
Proceedings of the conference on Design, automation and test in Europe: Proceedings
VFSim: concurrent fault simulation at register transfer level
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
Evolution of synthetic RTL benchmark circuits with predefined testability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Column-matching based mixed-mode test pattern generator design technique for BIST
Microprocessors & Microsystems
BenCGen: a digital circuit generation tool for benchmarks
Proceedings of the 21st annual symposium on Integrated circuits and system design
Implementation of low power adder design and analysis based on power reduction technique
Microelectronics Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate rank ordering of error candidates for efficient HDL design debugging
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Approximation refinement for interpolation-based model checking
VMCAI'08 Proceedings of the 9th international conference on Verification, model checking, and abstract interpretation
Coverage driven high-level test generation using a polynomial model of sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An evaluation of a slice fault aware tool chain
Proceedings of the Conference on Design, Automation and Test in Europe
Guided gate-level ATPG for sequential circuits using a high-level test generation approach
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Wire topology optimization for low power CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Feasibility analysis for robustness quantification by symbolic model checking
Formal Methods in System Design
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
FPGA logic synthesis using quantified boolean satisfiability
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
Dynamic property mining for embedded software
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Time-Constraint-Aware Optimization of Assertions in Embedded Software
Journal of Electronic Testing: Theory and Applications
Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
The influence of implementation type on dependability parameters
Microprocessors & Microsystems
Memory block based scan-BIST architecture for application-dependent FPGA testing
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Automatic generation of compact formal properties for effective error detection
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
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New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach