Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
A Test Pattern Generation Algorithm Exploiting Behavioral Information
ATS '98 Proceedings of the 7th Asian Test Symposium
Testing functional faults in VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
High-Level Observability for Effective High-Level ATPG
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient evaluation and vector generation method for observability-enhanced statement coverage
Journal of Computer Science and Technology
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The paper proposes a novel ATPG (Automatic Test Pattern Generation) method based on RTL (Register Transfer Level) behavioral descriptions in HDL (Hardware Description Language). The method is simulation-based. Firstly, it abstracts RTL behavioral descriptions to Process Controlling Trees (PCT)and Data Dependency Graphs (DDG), which are used for behavioral simulation and data tracing. Transfer faults are extracted from DDG edges, which compose a fault set needed for test generation. Then, simulation begins without specifying inputs in advance, and a request-echo strategy is used to fix some uncertain inputs if necessary. Finally, when the simulation ends, the partially fixed input sequence is the generated test sequence. The proposed request-echo strategy greatly reduces unnecessary backtracking, and always tries to cover uncovered transfer faults. Therefore, the proposed method is very efficient, and generates tests with good quality. Experimental results demonstrate that the proposed method is better than ARTIST in three aspects: (1) the CPU time is shorter by three orders of magnitude; (2) the test length is shorter by 52%; and (3) the fault coverage is higher by 0.89%.