A Testable Design of Logic Circuits Under Highly Observable Condition
IEEE Transactions on Computers - Special issue on fault-tolerant computing
High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Design Verification and Functional Testing of Finite State Machines
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
High-Level Observability for Effective High-Level ATPG
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A novel RTL behavioral description based ATPG method
Journal of Computer Science and Technology
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
IEEE Transactions on Computers
OCCOM-efficient computation of observability-based code coverage metrics for functional verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Coverage evaluation is indispensable for verification via simulation. As the functional complexity of modern design is increasing at a breathtaking pace, it is requisite to take observability into account. Unfortunately, nowadays coverage metrics taking observability into account are not very satisfactory. On the one hand, for the observability assessment algorithms proposed up to now, the overhead of computing is large, so they could not be integrated into simulation tools easily. On the other hand, the vector generation methods involving the metrics taking observability into account are not very efficient, and there exists a disconnection between these metrics and the vector generation process.In this paper, some original ideas for the problems above are presented. (1) Precise and concise abstract representations from HDL (Hardware Description Language) descriptions at RTL (Register Transfer Level) are presented to model observability information. (2) A novel observability evaluation method based on the proposed models is introduced. This method is more computationally efficient than prior efforts to assess observability and it could be integrated into compilers and simulators easily. (3) A new simulation vector generation procedure involving the observability-enhanced statement coverage metric is developed. The method is simulation-based and driven by the distribution of unobserved statements. During this procedure, the proposed algorithm always tries to cover all unobserved statements, and reduce unnecessary backtracking, so it is efficient. The methods proposed have been implemented as a prototype tool for VHDL designs, and the results on benchmarks show significant benefits.