Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
The complete guide to system testing
The complete guide to system testing
Software testing techniques (2nd ed.)
Software testing techniques (2nd ed.)
RISC: Acorn RISC machine family data manual
RISC: Acorn RISC machine family data manual
Validating discrete event simulations using event pattern mappings
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Automatic verification of pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
AVPGEN—a test generator for architecture verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling constraint generation for communicating processes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Design verification via simulation and automatic test pattern generation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Automatic generation of functional vectors using the extended finite state machine model
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An observability-based code coverage metric for functional simulation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Abstraction Techniques for Validation Coverage Analysis and Test Generation
IEEE Transactions on Computers
DAC '98 Proceedings of the 35th annual Design Automation Conference
User defined coverage—a tool supported methodology for design verification
DAC '98 Proceedings of the 35th annual Design Automation Conference
High-level design verification of microprocessors via error modeling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Trace Table Based Approach for Pipeline Microprocessor Verification
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
A Unified Framework for Design Validation and Manufacturing Test
Proceedings of the IEEE International Test Conference on Test and Design Validity
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Verification of Processor Microarchitectures
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Effectiveness of Microarchitecture Test Program Generation
IEEE Design & Test
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Automatic circuit extractor for HDL description using program slicing
Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An efficient evaluation and vector generation method for observability-enhanced statement coverage
Journal of Computer Science and Technology
Journal of Electronic Testing: Theory and Applications
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines
Proceedings of the conference on Design, automation and test in Europe
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
Abstractions for Model-Based Testing
Electronic Notes in Theoretical Computer Science (ENTCS)
A novel mutation-based validation paradigm for high-level hardware descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Design validation is becoming more and more a bottleneck in themicroprocessor design process. The difficulty of validation stemsfrom the complexity of the design, which requires searching anenormous space to check correctness. This is exacerbated by featuresfor enhancing performance, such as pipelines, which are becomingcommon in most microprocessors. This paper describes a newabstraction technique to handle this problem. Our solution is anovel method to identify the control states automatically fromthe processor HDL description and to extract an abstract finite statemachine model which preserves the behaviors of the design accurateto the clock cycle, so that the state space to be analyzed isdrastically reduced.This model is used to evaluate microarchitecture-level coverage ofvalidation tests. We also present validation test generation algorithmfor traversing state transition paths and covering snapshot and temporalevents. These abstract paths with a finite length, along withinformation about the instruction set, are used to generate system-leveltests. Results on example microprocessor models show the technique isefficient in finding bugs that other verification methods miss.