The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Digital Technical Journal - Special 10th anniversary issue
Architecture validation for processors
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Architectural Verification of Processors Using Symbolic Instruction Graphs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Improving coverage analysis and test generation for large designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
SIVA: A System for Coverage-Directed State Space Search
Journal of Electronic Testing: Theory and Applications
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On Design Validation Using Verification Technology
Journal of Electronic Testing: Theory and Applications
An Automatic Controller Extractor for HDL Descriptions at the RTL
IEEE Design & Test
Coverage Metrics for Functional Validation of Hardware Designs
IEEE Design & Test
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Coverage Metrics for Temporal Logic Model Checking
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
A Practical Approach to Coverage in Model Checking
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
12.1 Using Verification Technology for Validation Coverage Analysis and Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Smart diagnostics for configurable processor verification
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Coverage metrics for temporal logic model checking
Formal Methods in System Design
Clock domain crossing fault model and coverage metric for validation of SoC design
Proceedings of the conference on Design, automation and test in Europe
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
Improving functional verification of embedded systems using hierarchical composition and set theory
Proceedings of the 2009 ACM symposium on Applied Computing
Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In interactive behavioral synthesis, the designer can control the design process at every stage, including modifying the schedule of the design to improve its performance. In this paper, we present a methodology for performance optimization in interactive behavioral synthesis. Also proposed are several quality metrics and hints that can assist the user in utilizing the proposed methodology. When the user is optimizing the performance of the design, one important decision is the selection of a clock period. To facilitate clock selection by the user, we have developed an algorithm to estimate the effect of different clock periods on the execution time of the design. We have tested our methodology on several benchmarks. The experimental results support the proposed methodology by demonstrating an average improvement of 46.2% in design performance.