High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Validation coverage analysis for complex digital designs
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Enhancing simulation with BDDs and ATPG
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simulation vector generation from HDL descriptions for observability-enhanced statement coverage
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Improving coverage analysis and test generation for large designs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Functional vector generation for HDL models using linear programming and Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test sequence generation for controller verification and test with high coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Divide-and-conquer is a natural way to cope with the complexity of automatic testbench generation. The key to developing an effective divide-and-conquer approach is to identify the partitioning boundaries where interactions among divided components are minimized. The authors propose a novel design decomposition scheme and show how it can help improve the performance of constraint solving for test generation.