Writing testbenches: functional verification of HDL models

Teaching future verification engineers: the forgotten side of logic design

Proceedings of the 38th annual Design Automation Conference

A comparison of three verification techniques: directed testing, pseudo-random testing and property checking

Proceedings of the 39th annual Design Automation Conference

A Methodology for Large-Scale Hardware Verification

FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design

Coverage directed test generation for functional verification using bayesian networks

Proceedings of the 40th annual Design Automation Conference

Generating random solutions for constraint satisfaction problems

Eighteenth national conference on Artificial intelligence

A "Design for Verification" Methodology

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design

Stimuli Generation with Late Binding of Values

Proceedings of the conference on Design, automation and test in Europe - Volume 1

A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation

IEEE Design & Test

Probabilistic regression suites for functional verification

Proceedings of the 41st annual Design Automation Conference

An automatic testbench generation tool for a SystemC functional verification methodology

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Domain Strategy and Coverage Metric for Validation

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Smart diagnostics for configurable processor verification

Proceedings of the 42nd annual Design Automation Conference

Piparazzi: a test program generator for micro-architecture flow verification

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Enhancing the control and efficiency of the covering process [logic verification]

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Scheduling of transactions for system-level test-case generation

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Dynamic and formal verification of embedded systems: a comparative survey

International Journal of Parallel Programming

Scheduling-based test-case generation for verification of multimedia SoCs

Proceedings of the 43rd annual Design Automation Conference

A high-level requirements engineering methodology for electronic system-level design

Computers and Electrical Engineering

ChipDesign: from theory to real world

WCAE '07 Proceedings of the 2007 workshop on Computer architecture education

INTEG: a stochastic testing system for microprocessor verification

ICC'07 Proceedings of the 11th Conference on Proceedings of the 11th WSEAS International Conference on Circuits - Volume 11

TCN (train communication network) gateway for simulation

EHAC'05 Proceedings of the 4th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications

Embedded DSP Processor Design: Application Specific Instruction Set Processors

Embedded DSP Processor Design: Application Specific Instruction Set Processors

Verification of chip multiprocessor memory systems using a relaxed scoreboard

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture

Constraint-based random stimuli generation for hardware verification

IAAI'06 Proceedings of the 18th conference on Innovative applications of artificial intelligence - Volume 2

Holistic verification: myth or magic bullet?

Proceedings of the 46th Annual Design Automation Conference

An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC

Computers and Electrical Engineering

Using a constraint satisfaction formulation and solution techniques for random test program generation

IBM Systems Journal

Verification strategy for the Blue Gene/L chip

IBM Journal of Research and Development

Using linear programming techniques for scheduling-based random test-case generation

HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing

Using virtual coverage to hit hard-to-reach events

HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing

Research on setting up a simplified model in simulation

IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application

Functional qualification of TLM verification

Proceedings of the Conference on Design, Automation and Test in Europe

GCS: high-performance gate-level simulation with GP-GPUs

Proceedings of the Conference on Design, Automation and Test in Europe

A reuse approach for FPGA-based SDR waveforms

MILCOM'06 Proceedings of the 2006 IEEE conference on Military communications

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

Proceedings of the 48th Design Automation Conference

Facing the challenge of new design features: an effective verification approach

Proceedings of the 48th Design Automation Conference

Hardware design and simulation for verification

SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems