Automatic test program generation for pipelined processors
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Micro architecture coverage directed generation of test programs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-level test generation for design verification of pipelined microprocessors
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Multiprocessing design verification methodology for Motorola MPC74XX PowerPC microprocessor
Proceedings of the 37th Annual Design Automation Conference
A new verification methodology for complex pipeline behavior
Proceedings of the 38th annual Design Automation Conference
Adaptive test program generation: planning for the unplanned
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Stimuli Generation with Late Binding of Values
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A generic micro-architectural test plan approach for microprocessor verification
Proceedings of the 42nd annual Design Automation Conference
Preprocessing Expression-Based Constraint Satisfaction Problems for Stochastic Local Search
CPAIOR '07 Proceedings of the 4th international conference on Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
A novel approach for implementing microarchitectural verification plans in processor designs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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Because of their complexity, modern microprocessors need new tools that generate tests for micro-architectural events. Piparazzi is a test generator, developed at IBM, that generates (architectural) test programs for microarchitectural events. Piparazzi uses a declarative model of the micro-architecture and the user's definition of the required event to create an instance of a Constraint Satisfaction Problem (CSP). It then uses a dedicated CSP solver to generate a test program that covers the specific event. We show how Piparazzi yields significant improvements in covering micro-architectural events, by describing its technology and by exhibiting experimental results. Piparazzi has already been successful in finding both functional and performance bugs that could only be discovered using an exact micro-architectural model of the processor.