DAC '98 Proceedings of the 35th annual Design Automation Conference
Functional verification methodology for microprocessors using the Genesys test-program generator
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Model checking
Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
Art of Verification with VERA
Improving Test Quality Through Resource Reallocation
HLDVT '01 Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop (HLDVT'01)
Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
Generating concurrent test-programs with collisions for multi-processor verification
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Adaptive test program generation: planning for the unplanned
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
FPgen - a test generation framework for datapath floating-point verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Piparazzi: a test program generator for micro-architecture flow verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Industrial experience with test generation languages for processor verification
Proceedings of the 41st annual Design Automation Conference
A generic micro-architectural test plan approach for microprocessor verification
Proceedings of the 42nd annual Design Automation Conference
VLIW: a case study of parallelism verification
Proceedings of the 42nd annual Design Automation Conference
Depth-driven verification of simultaneous interfaces
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An SPU reference model for simulation, random test generation and verification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Test generation using SAT-based bounded model checking for validation of pipelined processors
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Functional test generation using property decompositions for validation of pipelined processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation
IEEE Transactions on Computers
Specification-driven directed test generation for validation of pipelined processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards Automating Simulation-Based Design Verification Using ILP
Inductive Logic Programming
Specification-based compaction of directed tests for functional validation of pipelined processors
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Functional test generation using design and property decomposition techniques
ACM Transactions on Embedded Computing Systems (TECS)
MMV: a metamodeling based microprocessor validation environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic constraint based test generation for behavioral HDL models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
Design validation of multithreaded architectures using concurrent threads evolution
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
POWER7: verification challenge of a multi-core processor
Proceedings of the 2009 International Conference on Computer-Aided Design
Programming and Computing Software
Using linear programming techniques for scheduling-based random test-case generation
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
Reaching coverage closure in post-silicon validation
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Advances in simultaneous multithreading testcase generation methods
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
A novel mutation-based validation paradigm for high-level hardware descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Facing the challenge of new design features: an effective verification approach
Proceedings of the 48th Design Automation Conference
Learning microarchitectural behaviors to improve stimuli generation quality
Proceedings of the 48th Design Automation Conference
Accelerating microprocessor silicon validation by exposing ISA diversity
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
Path-Based system level stimuli generation
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Checking architectural outputs instruction-by-instruction on acceleration platforms
Proceedings of the 49th Annual Design Automation Conference
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
IBM Journal of Research and Development
Proceedings of the 50th Annual Design Automation Conference
Automated generation of directed tests for transition coverage in cache coherence protocols
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Generating instruction streams using abstract CSP
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A novel approach for implementing microarchitectural verification plans in processor designs
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
Extensible environment for test program generation for microprocessors
Programming and Computing Software
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Historically, IBM's random test-program generation (RTPG) methodology has tightly coupled architectural information with the TPG tool. Model-based TPG removes this architecture dependency and provides a generic solution to functional testbench generation. Genesys-Pro, the second-generation model-based TPG tool, has many improvements over its predecessor, Genesys, including greater expressive power in the test template language and more constraint-solving processing power.