Journal of the ACM (JACM)
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Maintaining knowledge about temporal intervals
Communications of the ACM
Art of Verification with VERA
Design Verification with e
X-Gen: a random test-case generator for systems and SoCs
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Scheduling-based test-case generation for verification of multimedia SoCs
Proceedings of the 43rd annual Design Automation Conference
Introduction to Operations Research and Revised CD-ROM 8
Introduction to Operations Research and Revised CD-ROM 8
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon)
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Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which controls a stage in the processing of a media stream. Stimuli generation for such systems can be modeled as a scheduling problem that assigns data items to the processing elements of the system. Our work presents a linear programming (LP) modeling scheme for these scheduling problems. We implemented this modeling scheme as part of SoCVer, a stimuli generator for multimedia SoCs. Experimental results show that this LP-based scheme allows easier modeling and provides better performance than CSP-based engines, which are widely used for stimuli generation.