A BNF-based automatic test program generator for compatible microprocessor verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Stimuli Generation with Late Binding of Values
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Scheduling of transactions for system-level test-case generation
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Verification of the cell broadband engine™ processor
Proceedings of the 43rd annual Design Automation Conference
Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems
IBM Journal of Research and Development - POWER5 and packaging
Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation
IEEE Transactions on Computers
Intelligent interleaving of scenarios: a novel approach to system level test generation
Proceedings of the 44th annual Design Automation Conference
Constraint-based random stimuli generation for hardware verification
IAAI'06 Proceedings of the 18th conference on Innovative applications of artificial intelligence - Volume 2
Design validation of multithreaded architectures using concurrent threads evolution
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Using linear programming techniques for scheduling-based random test-case generation
HVC'06 Proceedings of the 2nd international Haifa verification conference on Hardware and software, verification and testing
IBM Journal of Research and Development
Facing the challenge of new design features: an effective verification approach
Proceedings of the 48th Design Automation Conference
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
EmGen: an automatic test-program generation tool for embedded IP cores
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Path-Based system level stimuli generation
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Generating instruction streams using abstract CSP
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A new test-generation methodology for system-level verification of production processes
HVC'12 Proceedings of the 8th international conference on Hardware and Software: verification and testing
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We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (SoC). X-Gen provides a framework and a set of building blocks for system-level test-case generation. At the core of this framework lies a system model, which consists of component types, their configuration, and the interactions between them. Building blocks include commonly used concepts such as memories, registers, and address translation mechanisms. Once a system is modeled, X-Gen provides a rich language for describing test cases. Through this language, users can specify requests that cover the full spectrum between highly directed tests to completely random ones. X-Gen is currently in preliminary use at IBM for the verification of two different designs - a high-end multi-processor server and a state-of-the-art SoC.