Nuts and bolts of core and SoC verification
Proceedings of the 38th annual Design Automation Conference
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Art of Verification with VERA
Top-level validation of system-on-chip in Esterel Studio
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
X-Gen: a random test-case generator for systems and SoCs
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Verification of the cell broadband engine™ processor
Proceedings of the 43rd annual Design Automation Conference
Scheduling-based test-case generation for verification of multimedia SoCs
Proceedings of the 43rd annual Design Automation Conference
Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems
IBM Journal of Research and Development - POWER5 and packaging
Overview of the Blue Gene/L system architecture
IBM Journal of Research and Development
Facing the challenge of new design features: an effective verification approach
Proceedings of the 48th Design Automation Conference
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Parallelism in system architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. We report on a method for system-level test case generation. This method relies on dynamic interleaving of scenarios from the core level or sub-system level. We discuss the relevance of this method for the system level. We also describe a tool that implements this method and show how it was used in IBM for system verification of the Xbox 360 chip and Power Management in the Cell processor, as well as verification of the pSeries eServers. We claim that this method shortened the system level verification cycle and allowed reuse in and across projects, which led to exposure of system-level bugs in a relatively short time.