Using embedded infrastructure IP for SOC post-silicon verification
Proceedings of the 40th annual Design Automation Conference
Synthesis of a Wireless Communication Analog Back-End Based on a Mismatch-Aware Symbolic Approach
Analog Integrated Circuits and Signal Processing
On compliance test of on-chip bus for SOC
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An automatic testbench generation tool for a SystemC functional verification methodology
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Verification of a Complex SoC: The PRO3 Case-Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Effective Co-Verification of IEEE 802.11a MAC/PHY Combining Emulation and Simulation Technology
ANSS '05 Proceedings of the 38th annual Symposium on Simulation
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Abstraction and refinement techniques in automated design debugging
Proceedings of the conference on Design, automation and test in Europe
Intelligent interleaving of scenarios: a novel approach to system level test generation
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Test Plan Generation for Concurrent Real-Time Systems Based on Zone Coverage Analysis
TestCom '08 / FATES '08 Proceedings of the 20th IFIP TC 6/WG 6.1 international conference on Testing of Software and Communicating Systems: 8th International Workshop
Formal Functional Verification of Device Drivers
VSTTE '08 Proceedings of the 2nd international conference on Verified Software: Theories, Tools, Experiments
Diagnosis and repair method of SoC memory
WSEAS Transactions on Circuits and Systems
Algebra-logical diagnosis model for SoC F-IP
WSEAS Transactions on Circuits and Systems
A succinct memory model for automated design debugging
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Spatial and temporal design debug using partial MaxSAT
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Optimal embedded repairing of SOC memory
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Embedded SOC F-IP diagnosis by using algebraic logical method
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Debugging strategies for mere mortals
Proceedings of the 46th Annual Design Automation Conference
High-speed post-layout logic simulation using quasi-static clock event evaluation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verifying VHDL designs with multiple clocks in SMV
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Distributed time, conservative parallel logic simulation on GPUs
Proceedings of the 47th Design Automation Conference
FEMU: a firmware-based emulation framework for SoC verification
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Automated design debugging with maximum satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From RTL to silicon: the case for automated debug
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Massively Parallel Logic Simulation with GPUs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards accelerating irregular EDA applications with GPUs
Integration, the VLSI Journal
Automatic test case generation with region-related coverage annotations for real-time systems
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Accelerating RTL simulation with GPUs
Proceedings of the International Conference on Computer-Aided Design
Path-Based system level stimuli generation
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Cohesive Coverage Management: Simulation Meets Formal Methods
Journal of Electronic Testing: Theory and Applications
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This book is a comprehensive guide to an overall SOC verification methodology; and indeed, it provides a snapshot of today's verification landscape and broadly outlines the safe pathways through the wilderness, avoiding the swamps and quicksand that lies waiting for the unwary.