Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
The C programming language
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Patterns for parallel programming
Patterns for parallel programming
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
Distributed time, conservative parallel logic simulation on GPUs
Proceedings of the 47th Design Automation Conference
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
SCGPSim: a fast SystemC simulator on GPUs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects
Proceedings of the Conference on Design, Automation and Test in Europe
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With the fast increasing complexity of integrated circuits, verification has become the bottleneck of today's IC design flow. In fact, over 70% of the IC design turn-around time can be spent on the verification process in a typical IC design project. Among various verification tasks, Register Transfer Level (RTL) simulation is the most widely used method to validate the correctness of digital IC designs. When simulating a large IC design with complicated internal behaviors (e.g., CPU cores running embedded software), RTL simulation can be extremely time consuming. Since RTL-to-layout is still the most prevalent IC design methodology, it is essential to speedup the RTL simulation process. Recently, General Purpose computing on Graphics Processing Units (GPGPU) is becoming a promising paradigm to accelerate computing-intensive workloads. A few recent works have demonstrated the effectiveness of using GPU to expedite gate and system level simulation tasks. In this work, we proposed an efficient GPU-accelerated RTL simulation framework. We introduce a methodology to translate Verilog RTL description into equivalent GPU source code so as to simulate circuit behavior on GPUs. In addition, a CMB based parallel simulation protocol is also adopted to provide a sufficient level of parallelism. Because RTL simulation lacks data-level parallelism, we also present a novel solution to use GPU as an efficient task-level parallel processor. Experimental results prove that our GPU based simulator outperforms a commercial sequential RTL simulator by over 20 fold.