Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
Speeding up distributed simulation using the time warp mechanism
EW 2 Proceedings of the 2nd workshop on Making distributed systems work
Parallel Logic Simulation Using Time Warp on Shared-Memory Multiprocessors
Proceedings of the 8th International Symposium on Parallel Processing
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Communication-efficient hardware acceleration for fast functional simulation
Proceedings of the 41st annual Design Automation Conference
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
Event-driven gate-level simulation with GP-GPUs
Proceedings of the 46th Annual Design Automation Conference
Efficient fault simulation on many-core processors
Proceedings of the 47th Design Automation Conference
Distributed time, conservative parallel logic simulation on GPUs
Proceedings of the 47th Design Automation Conference
Multicore parallelization of min-cost flow for CAD applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Parallel cross-layer optimization of high-level synthesis and physical design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Massively Parallel Logic Simulation with GPUs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards accelerating irregular EDA applications with GPUs
Integration, the VLSI Journal
GPU programming for EDA with OpenCL
Proceedings of the International Conference on Computer-Aided Design
Accelerating RTL simulation with GPUs
Proceedings of the International Conference on Computer-Aided Design
Multi-level Parallelism for Time- and Cost-Efficient Parallel Discrete Event Simulation on GPUs
PADS '12 Proceedings of the 2012 ACM/IEEE/SCS 26th Workshop on Principles of Advanced and Distributed Simulation
On the use of GP-GPUs for accelerating compute-intensive EDA applications
Proceedings of the Conference on Design, Automation and Test in Europe
RAG: an efficient reliability analysis of logic circuits on graphics processing units
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
FAST-GP: an RTL functional verification framework based on fault simulation on GP-GPUs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A GPU-based discrete event simulation kernel
Simulation
On the automatic generation of GPU-oriented software applications from RTL IPs
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
| Hi-index | 0.00 |
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely -- from high-level descriptions down to gate-level ones -- to validate several aspects of the design, particularly functional correctness. Despite development houses investing vast resources in the simulation task, particularly at the gate-level, it is still far from achieving the performance demands required to validate complex modern designs. In this work, we propose the first event-driven logic simulator accelerated by a parallel, general purpose graphics processor (GP-GPU). Our simulator leverages a gate-level event-driven design to exploit the benefits of the low switching activity that is typical of large hardware designs. We developed novel algorithms for circuit netlist partitioning and optimized for a highly-parallel GP-GPU host. Moreover, our flow is structured to extract the best simulation performance from the target hardware platform. We found that our experimental prototype could handle large, industrial scale designs comprised of millions of gates and deliver a 13x speedup on average over current commercial event-driven simulators.