Multicore parallelization of min-cost flow for CAD applications

  • Authors:

  • Yinghai Lu;Hai Zhou;Li Shang;Xuan Zeng

  • Affiliations:

  • State Key Laboratory of ASIC and System, Microelectronics Department, Fudan University, Shanghai, China;Northwestern University, Evanston, IL;Department of Electrical, Computer, and Energy Engineering, University of Colorado, Boulder, CO;State Key Laboratory of ASIC and System, Microelectronics Department, Fudan University, Shanghai, China

  • Venue:
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
  • Year:
  • 2010

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Abstract

Computational complexity has been the primary challenge of many very large scale integration computer-aided design (CAD) applications. The emerging multicore and many-core microprocessors have the potential to offer scalable performance improvements. How to explore the multicore resources to speed up CAD applications is thus a natural question but also a huge challenge for CAD researchers. This paper proposes a methodology to explore concurrency via nondeterministic transactional models, and to program them on multicore processors for CAD applications. Various run-time scheduling implementations on multicore shared-memory machines are discussed and the most efficient one is identified. The proposed methodology is applied to the min-cost flow problem which has been identified as the key problem in many design optimizations, from wire-length optimization in detailed placement to timing-constrained voltage assignment. A concurrent algorithm for min-cost flow has been developed based on the methodology. Experiments on voltage island generation in floorplanning have demonstrated its efficiency and scalable speedup over different numbers of cores.