Vector models for data-parallel computing
Vector models for data-parallel computing
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Introduction to algorithms
Iterative Methods for Sparse Linear Systems
Iterative Methods for Sparse Linear Systems
Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2)
Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2)
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Sparse matrix computations on manycore GPU's
Proceedings of the 45th annual Design Automation Conference
Parallelizing CAD: a timely research agenda for EDA
Proceedings of the 45th annual Design Automation Conference
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fast circuit simulation on graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Accelerating large graph algorithms on the GPU using CUDA
HiPC'07 Proceedings of the 14th international conference on High performance computing
The university of Florida sparse matrix collection
ACM Transactions on Mathematical Software (TOMS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An effective GPU implementation of breadth-first search
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
IP routing processing with graphic processors
Proceedings of the Conference on Design, Automation and Test in Europe
Multicore parallelization of min-cost flow for CAD applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Parallel cross-layer optimization of high-level synthesis and physical design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Gate-Level Simulation with GPU Computing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of N-queens solvers on graphics processors
APPT'11 Proceedings of the 9th international conference on Advanced parallel processing technologies
Towards accelerating irregular EDA applications with GPUs
Integration, the VLSI Journal
Proceedings of the 17th ACM SIGPLAN symposium on Principles and Practice of Parallel Programming
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Recently general purpose computing on graphic processing units (GPUs) is rising as an exciting new trend in high-performance computing. Thus it is appealing to study the potential of GPU for Electronic Design Automation (EDA) applications. However, EDA generally involves irregular data structures such as sparse matrix and graph operations, which pose significant challenges for efficient GPU implementations. In this paper, we propose highperformance GPU implementations for two important irregular EDA computing patterns, Sparse-Matrix Vector Product (SMVP) and graph traversal. On a wide range of EDA problem instances, our SMVP implementations outperform all published work and achieve a speedup of one order of magnitude over the CPU baseline. Upon such a basis, both timing analysis and linear system solution can be considerably accelerated. We also introduce a SMVP based formulation for Breadth-First Search and observe considerable speedup on GPU implementations. Our results suggest that the power of GPU computing can be successfully unleashed through designing GPU-friendly algorithms and/or re-organizing computing structures of current algorithms.