Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Power grid reduction based on algebraic multigrid principles
Proceedings of the 40th annual Design Automation Conference
Sparse matrix solvers on the GPU: conjugate gradients and multigrid
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Fast algorithms for IR drop analysis in large power grid
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Parallel domain decomposition for simulation of large-scale power grids
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A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power grid analysis using random walks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power Grid Analysis and Optimization Using Algebraic Multigrid
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the 47th Design Automation Conference
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ACM SIGDA Newsletter
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient incremental analysis of on-chip power grid via sparse approximation
Proceedings of the 48th Design Automation Conference
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Integration, the VLSI Journal
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
Fast Poisson solver preconditioned method for robust power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Power grid analysis with hierarchical support graphs
Proceedings of the International Conference on Computer-Aided Design
Fast thermal analysis on GPU for 3D-ICs with integrated microchannel cooling
Proceedings of the International Conference on Computer-Aided Design
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
Deterministic random walk preconditioning for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Efficient parallel power grid analysis via additive Schwarz method
Proceedings of the International Conference on Computer-Aided Design
PGT_SOLVER: an efficient solver for power grid transient analysis
Proceedings of the International Conference on Computer-Aided Design
Design analysis of IC power delivery
Proceedings of the International Conference on Computer-Aided Design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Large-scale flip-chip power grid reduction with geometric templates
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 50th Annual Design Automation Conference
Scalable power grid transient analysis via MOR-assisted time-domain simulations
Proceedings of the International Conference on Computer-Aided Design
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Integration, the VLSI Journal
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The challenging task of analyzing on-chip power (ground) distribution networks with multi-million node complexity and beyond is key to today's large chip designs. For the first time, we show how to exploit recent massively parallel single-instruction multiple-thread (SIMT) based graphics processing unit (GPU) platforms to tackle power grid analysis with promising performance. Several key enablers including GPU-specific algorithm design, circuit topology transformation, workload partitioning, performance tuning are embodied in our GPU-accelerated hybrid multigrid algorithm, GpuHMD, and its implementation. In particular, a proper interplay between algorithm design and SIMT architecture consideration is shown to be essential to achieve good runtime performance. Different from the standard CPU based CAD development, care must be taken to balance between computing and memory access, reduce random memory access patterns and simplify flow control to achieve efficiency on the GPU platform. Extensive experiments on industrial and synthetic benchmarks have shown that the proposed GpuHMD engine can achieve 100X runtime speedup over a state-of-the-art direct solver and be more than 15X faster than the CPU based multigrid implementation. The DC analysis of a 1.6 million-node industrial power grid benchmark can be accurately solved in three seconds with less than 50MB memory on a commodity GPU. It is observed that the proposed approach scales favorably with the circuit complexity, at a rate about one second per million nodes.