Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Power Supply Noise in SoCs: Metrics, Management, and Measurement
IEEE Design & Test
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On-die power grids: the missing link
Proceedings of the 47th Design Automation Conference
Modeling and design for beyond-the-die power integrity
Proceedings of the International Conference on Computer-Aided Design
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power grid analysis using random walks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power Grid Analysis and Optimization Using Algebraic Multigrid
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power integrity has become increasingly important for the designs in 32nm or below. This paper discusses a silicon-validated methodology for microprocessor power delivery modeling and simulation. There have been many prior works focusing on power delivery analysis and optimization. However, none of them provided a comprehensive modeling methodology with post-silicon data to validate the use of the models. In this paper, we present power delivery system models that are able to achieve less than 10% deviation from the supply noise measurements on a 32nm industrial microprocessor design. Our models are able to capture the unique impacts of on-die inductance, state dependent coupling capacitance and die-package interaction. Those impacts happen to be prominent for the designs in 32nm or below but were considered negligible or even not noted in earlier technology nodes. Comparisons were made to quantify the impacts of different modeling strategies on supply noise prediction accuracy. This specifically provides designers insights in selecting appropriate models for power delivery analysis. The impact of power delivery noise on timing margin was accurately estimated showing a good agreement to the worst-case jitter measurements.