High-speed signal propagation on lossy transmission lines
IBM Journal of Research and Development
Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Clocktree RLC extraction with efficient inductance modeling
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnect Analysis and Synthesis
Interconnect Analysis and Synthesis
Inductance calculations in a complex integrated circuit environment
IBM Journal of Research and Development
Three-dimensional inductance computations with partial element equivalent circuits
IBM Journal of Research and Development
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the impact of on-chip inductance on signal nets under the influence of power grid noise
Proceedings of the conference on Design, automation and test in Europe
Simultaneous signal and power routing under K model
Proceedings of the 2001 international workshop on System-level interconnect prediction
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
A library compatible driving point model for on-chip RLC interconnects
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Full-chip, three-dimensional, shapes-based RLC extraction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Practical considerations in RLCK crosstalk analysis for digital integrated circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A local circuit topology for inductive parasitics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An effective capacitance based driver output model for on-chip RLC interconnects
Proceedings of the 40th annual Design Automation Conference
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new multi-ramp driver model with RLC interconnect load
Proceedings of the 2004 international symposium on Physical design
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A metric for analyzing effective on-chip inductive coupling
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Shielding area optimization under the solution of interconnect crosstalk
Journal of Computer Science and Technology
Accurate loop self inductance bound for efficient inductance screening
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switch-factor based loop RLC modeling for efficient timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
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In this paper, based on simulations of top-level interconnects and CMOS devices of industrial 0.18 technology, the rules to screen out those inductive interconnects requiring more accurate RLC considerations, and the victim wires potentially having significant inductive noises are developed. The presented criteria constitute a tighter self-inductance screening rule than those found in previously published work. The 2x mutual-inductance screening rule is presented and verified. The differences in on-chip inductance consideration, the significant frequency of a trapezoidal pulse, and the circuit modeling of on-chip inductance are also discussed.