DAC '98 Proceedings of the 35th annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
Modeling and analysis of differential signaling for minimizing inductive cross-talk
Proceedings of the 38th annual Design Automation Conference
Properties of on-chip inductive current loops
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As higher operating frequencies are achieved in advanced digital designs, the influence of inductance on interconnect delays can no longer be ignored. A solution is proposed to prevent parasitic inductance effects on signal integrity by pre-estimating their impact during the early phases of the design flow. A pre-layout inductance modeling approach for on-chip advanced digital design interconnects, based on a relevant description of the current return path, is suggested. Representative structures for corner models are presented and assessed. They give minimal and maximal inductance value estimation. Finally, an original ring oscillator test structure is developed and implemented to highlight inductance impact on interconnect delay for a realistic digital environment. Silicon measurements match expected results and validate the presented corner models and methodology.