Return path selection for loop RL extraction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Accurate loop self inductance bound for efficient inductance screening
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The most common assumption for chip-level inductanceextraction is to restrict the current return path to the closestpower or ground lines. This paper shows that this assumptionis not necessarily valid for technologies beyond 0.1µm.The actual inductance can exceed twice the value that is extractedfrom the model considering only the nearest currentreturn paths. Analytical formulae to predict the worst caseself inductance are proposed to deal with the errors that resultfrom this assumption. These equations can be used asmetrics to decide the size of inductance extraction windowfor future CAD tools.