DAC '98 Proceedings of the 35th annual Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
Fast and accurate wire delay estimation for physical synthesis of large ASICs
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Convergence Properties of the Nelder--Mead Simplex Method in Low Dimensions
SIAM Journal on Optimization
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Managing on-chip inductive effects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed model shows an average error of 2%. A speedup of more than three orders of magnitude is obtained enabling our model to be fit for applications in inductance screening, inductance aware physical synthesis and prelayout inductance estimation.