GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Self-reforming routing for stochastic search in VLSI interconnection layout
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A solenoidal basis method for efficient inductance extraction
Proceedings of the 39th annual Design Automation Conference
A twisted-bundle layout structure for minimizing inductive coupling noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A local circuit topology for inductive parasitics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Electrical Modeling of Integrated-Package Power and Ground Distributions
IEEE Design & Test
Mutual inductance extraction and the dipole approximation
Proceedings of the 2004 international symposium on Physical design
Weibull Based Analytical Waveform Model
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Representative frequency for interconnect R(f)L(f)C extraction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Modeling skin and proximity effects with reduced realizable RL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect RL extraction at a single representative frequency
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Importance of volume discretization of single and coupled interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Accurate loop self inductance bound for efficient inductance screening
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk modeling for coupled RLC interconnects with application to shield insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
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It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines [7]. Furthermore, it is also understood that these circuits can be synthesized knowing only the high and the low frequency resistances and inductances [4]. Existing VLSI extraction tools however, are not efficient enough to solve for the frequency dependent resistances and inductances on large VLSI layouts, nor do they synthesize circuits suitable for timing analysis. We propose a rules-based method that efficiently and accurately captures the high and low frequency characteristics directly from layout shapes, and subsequently synthesizes a simple frequency independent ladder circuit suitable for timing analysis. We compare our results to other simulation results.