Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Hierarchical interconnect circuit models
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A twisted-bundle layout structure for minimizing inductive coupling noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
Implicit treatment of substrate and power-ground losses in return-limited inductance extraction
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SCORE: SPICE COmpatible Reluctance Extraction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
Journal of Electronic Testing: Theory and Applications
Effects of on-chip inductance on power distribution grid
Proceedings of the 2005 international symposium on Physical design
Fast simulation of VLSI interconnects
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
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With operating frequencies approaching the gigahertz range, inductance is becoming an increasingly important consideration in the design and analysis of on-chip interconnect. In this paper, we give a tutorial overview of the analysis and design issues related to on-chip inductance effects.We explain the complexity of the current flow in VLSI circuits. We discuss the applicability of the PEEC approach in a detailed circuit model of the signal and power grid interconnect, switching devices, power pads and the package. Fur-ther, we explain techniques that can be used to speed-up simulation of the large PEEC model. We then discuss a simplified model that uses the so-called loop inductance approach, and compare it with the detailed model.We present experimental results, obtained from simulations of industrial circuits, for both the PEEC and loop models. We also cover design techniques that can help tackle the on-chip inductance issues.