Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Efficient inductance extraction via windowing
Proceedings of the conference on Design, automation and test in Europe
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Modeling magnetic coupling for on-chip interconnect
Proceedings of the 38th annual Design Automation Conference
Modeling and analysis of regular symmetrically structured power/ground distribution networks
Proceedings of the 39th annual Design Automation Conference
On the efficacy of simplified 2D on-chip inductance models
Proceedings of the 39th annual Design Automation Conference
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Implicit treatment of substrate and power-ground losses in return-limited inductance extraction
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A local circuit topology for inductive parasitics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A precorrected-FFT method for simulating on-chip inductance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On-chip interconnect modeling by wire duplication
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Robust and passive model order reduction for circuits containing susceptance elements
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power network analysis using an adaptive algebraic multigrid approach
Proceedings of the 40th annual Design Automation Conference
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
An adaptive window-based susceptance extraction and its efficient implementation
Proceedings of the 40th annual Design Automation Conference
Analysis and Optimization of Power Grids
IEEE Design & Test
Electrical Modeling of Integrated-Package Power and Ground Distributions
IEEE Design & Test
SCORE: SPICE COmpatible Reluctance Extraction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Mutual inductance extraction and the dipole approximation
Proceedings of the 2004 international symposium on Physical design
CHIME: coupled hierarchical inductance model evaluation
Proceedings of the 41st annual Design Automation Conference
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-scale linear circuit simulation with an inversed inductance matrix
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
SPICE compatible circuit models for partial reluctance K
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Frequency-dependent reluctance extraction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Spatially distributed 3D circuit models
Proceedings of the 42nd annual Design Automation Conference
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast simulation of VLSI interconnects
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An efficient algorithm for 3-D reluctance extraction considering high frequency effect
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A metric for analyzing effective on-chip inductive coupling
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
RCLK-VJ network reduction with Hurwitz polynomial approximation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A wideband hierarchical circuit reduction for massively coupled interconnects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Comprehensive frequency dependent interconnect extraction and evaluation methodology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partial reluctance based circuit simulation is efficient and stable
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
An Improved AMG-based Method for Fast Power Grid Analysis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Stable and compact inductance modeling of 3-D interconnect structures
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A fast block structure preserving model order reduction for inverse inductance circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A fast band-matching technique for interconnect inductance modeling
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Generating stable and sparse reluctance/inductance matrix under insufficient conditions
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Speeding Up PEEC partial inductance computations using a QR-based algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switch-factor based loop RLC modeling for efficient timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
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On-chip inductance extraction and analysis is becoming increasing critical. Inductance extraction can be difficult, cumbersome and impractical on large designs as inductance depends on the current return path -- which is typically unknown prior to extracting and simulating the circuit model. In this paper, we propose a new circuit element, K, to model inductance effects, at the same time being easier to extract and analyze. K is defined as inverse of partial inductance matrix L, and has locality and sparsity normally associated with a capacitance matrix. We propose to capture inductance effects by directly extracting and simulating K, instead of partial inductance, leading to much more efficient procedure which is amenable to full chip extraction. This proposed approach has been verified through several simulation results.