Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Virtual screening: a step towards a sparse partial inductance matrix
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clocktree RLC extraction with efficient inductance modeling
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Efficient inductance extraction via windowing
Proceedings of the conference on Design, automation and test in Europe
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Full-chip, three-dimensional, shapes-based RLC extraction
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Equipotential shells for efficient inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Throughput-driven IC communication fabric synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
Mutual inductance extraction and the dipole approximation
Proceedings of the 2004 international symposium on Physical design
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Stable and compact inductance modeling of 3-D interconnect structures
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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Full three-dimensional (3D) inductance models of on-chip interconnect contain an extremely large number of forward coupling terms. It is therefore desirable to use a two-dimensional (2D) approximation in which forward couplings are not included. Unlike capacitive coupling, however, truncating mutual inductance terms can result in loss of accuracy and even instability. This paper investigates whether ignoring forward couplings is an acceptable choice for all good IC designs or if full 3D models are necessary in certain on-chip interconnect configurations. We show that the significance of the forward coupling inductance depends on various aspects of the design.