Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
On the efficacy of simplified 2D on-chip inductance models
Proceedings of the 39th annual Design Automation Conference
Impedance characteristics of power distribution grids in nanoscale integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power grid analysis using random walks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
Off-chip decoupling capacitor allocation for chip package co-design
Proceedings of the 44th annual Design Automation Conference
Power Supply Noise in SoCs: Metrics, Management, and Measurement
IEEE Design & Test
Parallel domain decomposition for simulation of large-scale power grids
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Heuristic power/ground network and floorplan co-design method
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Speedpath prediction based on learning from a small set of examples
Proceedings of the 45th annual Design Automation Conference
Enhancing beneficial jitter using phase-shifted clock distribution
Proceedings of the 13th international symposium on Low power electronics and design
Efficient representation and analysis of power grids
Proceedings of the conference on Design, automation and test in Europe
Effective radii of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Silicon feedback to improve frequency of high-performance microprocessors: an overview
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Power distribution paths in 3-D ICS
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Clock-tree synthesis for low-EMI design
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Decoupling capacitance efficient placement for reducing transient power supply noise
Proceedings of the 2009 International Conference on Computer-Aided Design
Verification and codesign of the package and die power delivery system using wavelets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-die power grids: the missing link
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient decoupling capacitance optimization using piecewise polynomial models
Proceedings of the Conference on Design, Automation and Test in Europe
EMC-aware design on a microcontroller for automotive applications
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient simulation of power grids
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Parallel and scalable transient simulator for power grids via waveform relaxation (PTS-PWR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Layout of decoupling capacitors in IP blocks for 90-nm CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated di/dt stressmark generation for microprocessor power delivery networks
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Efficient incremental analysis of on-chip power grid via sparse approximation
Proceedings of the 48th Design Automation Conference
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
Power grid effects and their impact on-die
Proceedings of the International Conference on Computer-Aided Design
Overview of vectorless/early power grid verification
Proceedings of the International Conference on Computer-Aided Design
AUDIT: Stress Testing the Automatic Way
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Decentralized and passive model order reduction of linear networks with massive ports
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and analysis of power distribution networks in 3-D ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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Much research has been done lately concerning analysis and optimization techniques for on-chip power grid networks.However, all of these approaches assume a particular model or behavior of the power delivery.In this paper, we describe the first detailed full-die dynamic model of an industrial microprocessor design, including package and non-uniform decap distribution.This model is justified from the ground up using a full-wave model and then increasingly larger but less detailed models with only the irrelevant elements removed.Using these models we show that there is little impact of on-die inductance in such a design, and that the package is critical to understanding resonant properties of the grid.We also show that transient effects are sensitive to non-uniform de-cap distribution and that locality is a tight function of frequency and of the package-die resonance, producing newly explained localized resonant effects.Specifically, all of these points have impact on what kind of analysis and optimization are required from CAD.