Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources
Proceedings of the 37th Annual Design Automation Conference
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for power grid design
Proceedings of the 2005 international symposium on Physical design
Partitioning-based approach to fast on-chip decap budgeting and minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Efficient early stage resonance estimation techniques for C4 package
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Power distribution techniques for dual VDD circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
High accurate pattern based precondition method for extremely large power/ground grid analysis
Proceedings of the 2006 international symposium on Physical design
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A sliding window scheme for accurate clock mesh analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Large power grid analysis using domain decomposition
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
Partitioning-based decoupling capacitor budgeting via sequence of linear programming
Integration, the VLSI Journal
Early power grid verification under circuit current uncertainties
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Large scale P/G grid transient simulation using hierarchical relaxed approach
Integration, the VLSI Journal
Power Grid Physics and Implications for CAD
IEEE Design & Test
A geometric approach for early power grid verification using current constraints
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parallel domain decomposition for simulation of large-scale power grids
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Module assignment for pin-limited designs under the stacked-Vdd paradigm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 international symposium on Physical design
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Effective radii of on-chip decoupling capacitors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Incremental and on-demand random walk for iterative power distribution network analysis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
GPU friendly fast Poisson solver for structured power grid network analysis
Proceedings of the 46th Annual Design Automation Conference
Fast vectorless power grid verification using an approximate inverse technique
Proceedings of the 46th Annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Locality-driven parallel power grid optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-die power grids: the missing link
Proceedings of the 47th Design Automation Conference
Incremental solution of power grids using random walks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Locality-Driven Parallel Static Analysis for Power Delivery Networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel and scalable transient simulator for power grids via waveform relaxation (PTS-PWR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient incremental analysis of on-chip power grid via sparse approximation
Proceedings of the 48th Design Automation Conference
Power grid verification using node and branch dominance
Proceedings of the 48th Design Automation Conference
Fast algorithms for IR voltage drop analysis exploiting locality
Proceedings of the 48th Design Automation Conference
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
Efficient algorithms for fast IR drop analysis exploiting locality
Integration, the VLSI Journal
Timing yield analysis considering process-induced temperature and supply voltage variations
Microelectronics Journal
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
Placement optimization of power supply pads based on locality
Proceedings of the Conference on Design, Automation and Test in Europe
Large-scale flip-chip power grid reduction with geometric templates
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable vectorless power grid current integrity verification
Proceedings of the 50th Annual Design Automation Conference
Decentralized and passive model order reduction of linear networks with massive ports
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IR-drop in on-chip power distribution networks of ICs with nonuniform power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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Full-chip power grid analysis is time consuming. Several techniques have been proposed to tackle the problem but typically they deal with the power grid as a whole or partition at unnatural boundaries. Using a locality effect under flip-chip packaging, we propose a natural partitioning approach based on overlapping power grid "shells". The technique makes more efficient any previous simulation techniques that are polynomial in grid size. It is also parallelizable and therefore extremely fast. Using complete partitions gives no loss of accuracy compared to a full matrix solution, while lesser partitions are conservative for droop and current. Results on a recent Pentium/spl reg/ microprocessor design show excellent speed and accuracy.