Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources

Decoupling capacitance allocation for power supply noise suppression

Proceedings of the 2001 international symposium on Physical design

HiPRIME:: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery

Proceedings of the 39th annual Design Automation Conference

Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Fast flip-chip power grid analysis via locality and grid shells

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Relaxed hierarchical power/ground grid analysis

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance

Proceedings of the 2006 international symposium on Physical design

High accurate pattern based precondition method for extremely large power/ground grid analysis

Proceedings of the 2006 international symposium on Physical design

Model order reduction of linear networks with massive ports via frequency-dependent port packing

Proceedings of the 43rd annual Design Automation Conference

Large scale P/G grid transient simulation using hierarchical relaxed approach

Integration, the VLSI Journal

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

FEKIS: a fast architecture-level thermal analyzer for online thermal regulation

Proceedings of the 18th ACM Great Lakes symposium on VLSI

DeMOR: decentralized model order reduction of linear networks with massive ports

Proceedings of the 45th annual Design Automation Conference

ETBR: extended truncated balanced realization method for on-chip power grid network analysis

Proceedings of the conference on Design, automation and test in Europe

Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Incremental and on-demand random walk for iterative power distribution network analysis

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Statistical analysis of large on-chip power grid networks by variational reduction scheme

Integration, the VLSI Journal

Scalable analysis of mesh-based clock distribution networks using application-specific reduced order modeling

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Accurate direct and indirect on-chip temperature sensing for efficient dynamic thermal management

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009

Efficient power grid integrity analysis using on-the-fly error check and reduction

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

SWAN: high-level simulation methodology for digital substrate noise generation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Fast timing analysis of clock networks considering environmental uncertainty

Integration, the VLSI Journal

Deterministic random walk preconditioning for power grid analysis

Proceedings of the International Conference on Computer-Aided Design

Decentralized and passive model order reduction of linear networks with massive ports

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Scalable power grid transient analysis via MOR-assisted time-domain simulations

Proceedings of the International Conference on Computer-Aided Design

Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms

Proceedings of the International Conference on Computer-Aided Design