Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources
Proceedings of the 37th Annual Design Automation Conference
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
On the interaction of power distribution network with substrate
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Fast 3-D inductance extraction in lossy multi-layer substrate
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Characterizing Substrate Coupling in Deep-Submicron Designs
IEEE Design & Test
Robust and passive model order reduction for circuits containing susceptance elements
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
Proceedings of the conference on Design, automation and test in Europe
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
INDUCTWISE: inductance-wise interconnect simulator and extractor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPRIM: structure-preserving reduced-order interconnect macromodeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A fast block structure preserving model order reduction for inverse inductance circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Substrate model extraction using finite differences and parallel multigrid
Integration, the VLSI Journal
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The recent demand for system-on-chip RF mixed-signal designand aggressive supply-voltage reduction require chip-level accurateanalysis of both the substrate and power delivery systems.Together with the rising frequency, low-k dielectric, copper interconnects,and high conductivity substrate, the inductance effectsraised serious concern recently.However, the increasing designcomplexity creates tremendous challenges for chip-level power-deliverysubstrate co-analysis.In this paper, we propose a noveland efficient reluctance-based passive model order reduction techniqueto serve these tasks.Our work, SuPREME(Substrate andPower-delivery Reluctance-Enhanced Macromodel Evaluation) notonly greatly reduces the computational complexity of previousreluctance-based model order algorithms but is also capable ofhandling large number of noise sources efficiently.To facilitatethe analysis of inductive substrate return paths and evaluate thehigh-frequency substrate coupling effects, we derive a novel RLKCsubstrate model from Maxwell's equations for the first time.Experimentalresults demonstrate the superior runtime and accuracyof SuPREME compared to the traditional MNA-based simulation.