Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On-chip interconnect modeling by wire duplication
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
An adaptive window-based susceptance extraction and its efficient implementation
Proceedings of the 40th annual Design Automation Conference
SCORE: SPICE COmpatible Reluctance Extraction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SPICE compatible circuit models for partial reluctance K
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Frequency-dependent reluctance extraction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Spatially distributed 3D circuit models
Proceedings of the 42nd annual Design Automation Conference
An efficient algorithm for 3-D reluctance extraction considering high frequency effect
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
RCLK-VJ network reduction with Hurwitz polynomial approximation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Partial reluctance based circuit simulation is efficient and stable
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Stable and compact inductance modeling of 3-D interconnect structures
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A fast band-matching technique for interconnect inductance modeling
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the International Conference on Computer-Aided Design
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On-chip inductance extraction is difficult due to the global effect of inductance, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore, it is well known that simply discarding smallest terms to sparsify the inductance matrix can render the partial inductance matrix indefinite and result in an unstable circuit model. Recently a new circuit element, K , has been introduced to capture global effect of inductance by evaluating a corresponding sparse K matrix [1]. However, the reason that K has such local properties is not clear, and the positive semi-definiteness of the corresponding sparse K matrix is not proved. In this paper, we present the physical interpretation of K. Based on the physical interpretation, we explain why the faraway mutual K can be ignored (locality) and prove that after ignoring faraway mutual K ,the resultant K matrix is positive definite (stability). Together with a RKC equivalent circuit model, the locality and stability enables us to simulate RKC circuit directly and efficiently for real circuits. A new circuit simulation tool, KSim, has been developed by incorporating the new circuit element K into Berkeley SPICE. The RKC simulation matches better with the full partial inductance matrix simulation with significant less computing time and memory usage, compared to other proposed methods, such as shift-truncate method [2, 3].