Fast approximation of the transient response of Lossy Transmision Line Trees
DAC '93 Proceedings of the 30th international Design Automation Conference
DAC '93 Proceedings of the 30th international Design Automation Conference
Modification of the minimum-degree algorithm by multiple elimination
ACM Transactions on Mathematical Software (TOMS)
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 37th Annual Design Automation Conference
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Computer Solution of Large Sparse Positive Definite
Computer Solution of Large Sparse Positive Definite
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multigrid-like technique for power grid analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Hierarchical Modeling and Simulation of Large Analog Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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We propose a new linear network reduction algorithm based on a generalized Y-Δ transformation technique in s-domain. Resultant admittance is kept as a rational function of s with a dramatically reduced order. Yet it preserves low-order terms of exact admittance evaluated with traditional symbolic analysis. Stability of transfer functions derived from reduced-order admittance is guaranteed via a Hurwitz polynomial approximation. Such low-order transfer functions are used in pole analysis and time domain waveform evaluation in response to any input signal.