Simulating lossy interconnect with high frequency nonidealities in linear time
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An AWE technique for fast printed circuit board delays
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Prediction of interconnect delay in logic synthesis
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Delay Models for MCM Interconnects when Response is Non-Monotone
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Gate delay calculation considering the crosstalk capacitances
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Calculating the effective capacitance for the RC interconnect in VDSM technologies
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
RCLK-VJ network reduction with Hurwitz polynomial approximation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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