On the stability of moment-matching approximations in asymptotic waveform evaluation
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fast approximation of the transient response of Lossy Transmision Line Trees
DAC '93 Proceedings of the 30th international Design Automation Conference
Extending moment computation to 2-port circuit representations
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Equivalent Elmore delay for RLC trees
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Realizable reduction for RC interconnect circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Polynomials and Linear Control Systems
Polynomials and Linear Control Systems
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Equivalent Waveform Propagation for Static Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Shielding effect of on-chip interconnect inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a new relizable reduced order modeling technique for RLC interconnect trees. Both lumped and distributed wire models can be used with this technique. Provable stability is achieved by using Hurwitz polynomials. Moment computation process is avoided but moments can still be matched implicitly. In experiments, the proposed Hurwitz three-pole model can accurately and efficiently capture inductive effect for both near end and far end nodes.