A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
A unified design methodology for CMOS tapered buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New efficient algorithms for computing effective capacitance
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient analytical model of coupled on-chip RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An "effective" capacitance based delay metric for RC interconnect
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
CMOS gate delay models for general RLC loading
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Efficient Gate Delay Modeling for Large Interconnect Loads
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Fault tolerant bus architecture for deep submicron based processors
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
Wire shaping of RLC interconnects
Integration, the VLSI Journal
Shielding effect of on-chip interconnect inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. The effective capacitance of an RLC load driven by a CMOS inverter is analytically modeled. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall signal propagation delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, thereby reducing the dynamic power dissipation. A reduction in power of 17% and area of 29% is achieved for an example circuit.