High-level synthesis under multi-cycle interconnect delay
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
Frequency Characteristics of High Speed Power Distribution Grids
Analog Integrated Circuits and Signal Processing
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simplified delay design guidelines for on-chip global interconnects
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Switch-Factor Based Loop RLC Modeling for Efficient Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimum wire sizing of RLC interconnect with repeaters
Integration, the VLSI Journal
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Wire shaping of RLC interconnects
Integration, the VLSI Journal
Voltage-mode driver preemphasis technique for on-chip global buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Including inductance in static timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects
Microelectronics Journal
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A 32-Gb/s on-chip bus with driver pre-emphasis signaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An analytical approach to dynamic crosstalk in coupled interconnects
Microelectronics Journal
Reducing signal timing variations in inter-core busses
Integration, the VLSI Journal
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Exponentially tapered h-tree clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Equivalent circuit model of on-wafer CMOS interconnects for RFICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switch-factor based loop RLC modeling for efficient timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Shielding effect of on-chip interconnect inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quasi-resonant interconnects: a low power, low latency design methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and modeling of energy consumption in RLC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A closed-form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful criterion. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25-/spl mu/m IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this paper is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect.